1. Field of the Invention
The present invention relates to a semiconductor memory device and method thereof, and more particularly, to an output driver and method thereof.
2. Description of the Related Art
FIG. 1 illustrates a conventional differential input/output driver 100. Referring to FIG. 1, the differential input/output driver 100 may compare input signals IN1 and IN2 and may output a result of the comparison as a data input/output signal DQ and a complementary data input/output signal DQB. The differential input/output driver 100 may include a first NMOS transistor 101 having a gate receiving a first input signal IN1 and a second NMOS transistor 102 having a gate receiving a second input signal IN2. Sources of the first and second NMOS transistors 101 and 102 may be connected to a ground voltage VSS via a tail current source 105. Drains of the first and second NMOS transistors 101 and 102 may be connected to a power supply voltage VCC via first and second resistors 103 and 104, respectively, which may output the data input/output signal DQ and the complementary data input/output signal DQB, respectively.
FIG. 2 illustrates a graph of an amplitude of a current IDRV of the current source 105 of FIG. 1. As shown in FIG. 2, the current IDRV of the current source 105 may be relatively constant irrespective of an operating frequency FREQ.
FIG. 3 illustrates waveforms of the data input/output signal DQ and the complementary data input/output signal DQB at a higher-speed data rate and a lower-speed data rate of the differential input/output driver 100 of FIG. 1. Referring to FIG. 3, a slew rate of the data input/output signal DQ and the complementary data input/output signal DQB at the higher-speed data rate may be similar to a slew rate at the lower-speed data rate. The slew rate of a waveform may refer to a time required for a transition between a first logic level (e.g., a higher logic level, a lower logic level, etc.) and a second logic level (e.g., a lower logic level, a higher logic level, etc.). If the lower-speed data rate is used by the differential input/output driver 100, the integrity or swing width of the data input/output signal DQ and the complementary data input/output signal DQB may be higher.
If an output driver (e.g., the differential input/output driver 100) operates at the lower-speed data rate, a swing width between signals may be reduced. The reduced swing width may not negatively affect a discrimination between signal levels and power consumption in the output driver may thereby be reduced.
However, conventional output drivers (e.g., the differential input/output driver 100) may typically be set to consume a given amount of power (e.g., for a lower speed date rate, for a higher speed date rate, etc.) and may not change the power consumption during operation. Thus, conventional output drivers may be data-rate specific with respect to power consumption.